Espressif Systems /ESP32-C6 /EXTMEM /L2_CACHE_ACS_CNT_INT_CLR

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Interpret as L2_CACHE_ACS_CNT_INT_CLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (L2_IBUS0_OVF_INT_CLR)L2_IBUS0_OVF_INT_CLR 0 (L2_IBUS1_OVF_INT_CLR)L2_IBUS1_OVF_INT_CLR 0 (L2_IBUS2_OVF_INT_CLR)L2_IBUS2_OVF_INT_CLR 0 (L2_IBUS3_OVF_INT_CLR)L2_IBUS3_OVF_INT_CLR 0 (L2_DBUS0_OVF_INT_CLR)L2_DBUS0_OVF_INT_CLR 0 (L2_DBUS1_OVF_INT_CLR)L2_DBUS1_OVF_INT_CLR 0 (L2_DBUS2_OVF_INT_CLR)L2_DBUS2_OVF_INT_CLR 0 (L2_DBUS3_OVF_INT_CLR)L2_DBUS3_OVF_INT_CLR

Description

Cache Access Counter Interrupt clear register

Fields

L2_IBUS0_OVF_INT_CLR

The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache.

L2_IBUS1_OVF_INT_CLR

The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache.

L2_IBUS2_OVF_INT_CLR

Reserved

L2_IBUS3_OVF_INT_CLR

Reserved

L2_DBUS0_OVF_INT_CLR

The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache.

L2_DBUS1_OVF_INT_CLR

The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache.

L2_DBUS2_OVF_INT_CLR

Reserved

L2_DBUS3_OVF_INT_CLR

Reserved

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