Cache Access Counter Interrupt clear register
L2_IBUS0_OVF_INT_CLR | The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache. |
L2_IBUS1_OVF_INT_CLR | The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache. |
L2_IBUS2_OVF_INT_CLR | Reserved |
L2_IBUS3_OVF_INT_CLR | Reserved |
L2_DBUS0_OVF_INT_CLR | The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache. |
L2_DBUS1_OVF_INT_CLR | The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache. |
L2_DBUS2_OVF_INT_CLR | Reserved |
L2_DBUS3_OVF_INT_CLR | Reserved |